1. Field of the Invention
This invention relates to a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
MIS transistors are miniaturized and the gate lengths (channel lengths) thereof are made shorter. As the channel length becomes shorter, a punch-through phenomenon more easily tends to occur between the source and drain, and degradation of the transistor characteristic, for example, an increase in the leakage current will be caused.
In order to solve the above problem, a MIS transistor (Gate-All-Around structure MIS transistor) having an island-form semiconductor structure formed with a rectangular parallelepiped form on a substrate and surrounded by a gate electrode is proposed in a document 1 (J. P. Colinge et al., “SILICON-ON-INSULATOR ‘GATE-ALL-AROUND DEVICE’”, IEDM 1990, 25. 4, pp. 595–598). The MIS transistor is formed as follows. First, an island-form semiconductor structure is formed on a buried oxide film (BOX film). Then, the buried oxide film is etched by the use of a photoresist mask to form a cavity in a region directly under a channel forming region of the island-form semiconductor structure and a region around the above region. Next, a gate electrode material film is formed on the entire surface containing the cavity and the gate electrode material film is patterned to form a gate electrode which crosses the island-form semiconductor structure. Thus, the gate electrode which surrounds the channel forming region of the island-form semiconductor structure is formed. Since the island-form semiconductor structure also functions as an etching mask when the gate electrode material film is patterned, the gate electrode is formed to have extension portions in the cavity under the source and drain regions.
However, in the above proposal, the cavity and gate electrode are formed by the use of lithography technology. In lithography technology, since an alignment error occurs, a gate electrode pattern will be formed in position shifted from the center of the cavity pattern. As a result, the width of the extension portion of the gate electrode which lies under the source region becomes greatly different from the width of the extension portion thereof lying under the drain region. Therefore, only one of the overlap capacitance between the gate and source and the overlap capacitance between the gate and drain becomes larger, having a bad effect on the characteristic of the MIS transistor. Further, it is necessary to form a cavity pattern of large size when taking a margin for the alignment error into consideration and this leads to an increase in the overlap capacitance.
Further, a MIS transistor (Omega-Fin structure MIS transistor) having an island-form semiconductor structure surrounded by a gate electrode except the central portion of the undersurface of the island-form semiconductor structure is proposed in a document 2 (Fu-Liang Yang et al., “25 nm CMOS Omega FETs”, IEDM 2002, 10. 3, pp. 255–258). The MIS transistor is formed as follows. First, an island-form semiconductor structure is formed on a buried oxide film. Then, the buried oxide film is etched with the island-form semiconductor structure used as a mask to form a depression portion in the buried oxide film. At this time, the buried oxide film under the end portion of the island-form semiconductor structure is also etched to from an undercut portion under the island-form semiconductor structure. Next, a gate electrode material film is formed on the entire surface containing the undercut portion and the gate electrode material film is patterned to form a gate electrode which crosses the island-form semiconductor structure.
In the above proposal, the gate electrode is not formed in a position corresponding to the undercut portion under the source and drain regions. That is, unlike the proposal of the document 1, the gate electrode has no extension portion under the source and drain regions. When the source/drain region is formed by ion implantation, the distance between the source and drain regions is generally longer in the lower portion of the island-form semiconductor structure than in the upper portion thereof. In the document 2, since the gate electrode has no extension portion under the source and drain regions, offsets occur between the gate electrode and the source region and between the gate electrode and the drain region to significantly degrade the characteristics of the MIS transistor. Further, in the above proposal, since the undercut portion is formed in the entire portion under the island-form semiconductor structure, it is difficult to sufficiently fixedly hold the island-form semiconductor structure and there occurs a problem that the island-form semiconductor structure will fall down in the manufacturing process.
Thus, from the viewpoint of preventing occurrence of the punch-through phenomenon between the source and drain, Gate-All-Around structure MIS transistors and Omega-Fin structure MIS transistors are proposed. However, conventional MIS transistors with the above structures have a problem that the positional relationship between the gate electrode and the source/drain region cannot be optimized. Thus, it is difficult to attain a semiconductor device which has excellent characteristics and reliability.